EP2A25F672I7N vs EP2A25F672I-9 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP2A25F672I7N sa pamamagitan ng Intel at EP2A25F672I-9 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP2A25F672I7N EP2A25F672I-9
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family APEX II APEX II
Logic Elements (Cells) 24,320 —
Typical Gate Count 900,000 —
Maximum Internal Frequency 500 MHz —
Process Technology 0.15 µm CMOS 0.18 µm CMOS
Core Supply Voltage 1.5 V —
Packhaging 672-ball FC-FBGA 672-pin FCBGA (FineLine BGA)
Pin/Ball Count 672 —
Uri ng Pagpapasok Surface Mount (BGA) Surface Mount (BGA)
Operating Temperature Grade Industrial (I) Industrial (-40 °C to +100 °C junction)
Speed Grade 7 -9
Configuration Interface JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel —
Design Software Quartus II —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Katayuan ng Lifecycle Not Recommended for New Designs (NRND) —
Logic Elements (typical) — 25,000
Maximum System Gates — [DATA_NEEDED: maximum system gates]
Embedded System Blocks (ESB) Memory — 1,125 Kbits
Maximum User I/O Pins — [DATA_NEEDED: maximum user I/O pins]
Number of PLLs — 4
Core Voltage — 1.5 V / 1.8 V (speed-grade dependent)
Level ng Sensitivity sa Asid ng Moisture (MSL) — 3 (per Vyrian listing)
Peak Reflow Temperature — 220 °C (per Vyrian listing)
Configuration Method — JTAG / serial configuration EPROM
Supported I/O Standards — LVTTL, LVCMOS, LVDS, PCI
Legacy Status — Obsolete - consult Altera / Intel FPGA archive for documentation

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