EP2A25F672I7N vs EP2A25F672I-9 比較
詳細並排比較 EP2A25F672I7N 由 Intel 與 EP2A25F672I-9 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2A25F672I7N | EP2A25F672I-9 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | APEX II | APEX II |
| Logic Elements (Cells) | 24,320 | — |
| Typical Gate Count | 900,000 | — |
| Maximum Internal Frequency | 500 MHz | — |
| Process Technology | 0.15 µm CMOS | 0.18 µm CMOS |
| Core Supply Voltage | 1.5 V | — |
| 封裝 | 672-ball FC-FBGA | 672-pin FCBGA (FineLine BGA) |
| Pin/Ball Count | 672 | — |
| 安裝類型 | Surface Mount (BGA) | Surface Mount (BGA) |
| Operating Temperature Grade | Industrial (I) | Industrial (-40 °C to +100 °C junction) |
| Speed Grade | 7 | -9 |
| Configuration Interface | JTAG (IEEE 1149.1), Passive Serial, Fast Passive Parallel | — |
| Design Software | Quartus II | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| 生命週期狀態 | Not Recommended for New Designs (NRND) | — |
| Logic Elements (typical) | — | 25,000 |
| Maximum System Gates | — | [DATA_NEEDED: maximum system gates] |
| Embedded System Blocks (ESB) Memory | — | 1,125 Kbits |
| Maximum User I/O Pins | — | [DATA_NEEDED: maximum user I/O pins] |
| Number of PLLs | — | 4 |
| Core Voltage | — | 1.5 V / 1.8 V (speed-grade dependent) |
| 濕度敏感等級 (MSL) | — | 3 (per Vyrian listing) |
| Peak Reflow Temperature | — | 220 °C (per Vyrian listing) |
| Configuration Method | — | JTAG / serial configuration EPROM |
| Supported I/O Standards | — | LVTTL, LVCMOS, LVDS, PCI |
| Legacy Status | — | Obsolete - consult Altera / Intel FPGA archive for documentation |