EP3SE260F1517I4N vs EP3SE260H780C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE260F1517I4N sa pamamagitan ng Intel at EP3SE260H780C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE260F1517I4N - Stratix III E FPGA, 255K LE, 1517-BGA | Intel
EP3SE260F1517I4N ⚠ Huling PagbiliIntel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP3SE260F1517I4N | EP3SE260H780C3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Aktibo |
| Series | Stratix III E | Stratix® III E |
| Logic Elements | 255,000 | — |
| Embedded Memory Bits | 16,672,768 bits | — |
| Embedded Memory (M9K/M144K blocks) | [DATA_NEEDED: total Kbits and block count] | — |
| User I/O Pins | 976 | — |
| Transceivers | [DATA_NEEDED: number of full-duplex channels] | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| Transceiver Data Rate | 600 Mbps to 6.375 Gbps | — |
| DSP Blocks | [DATA_NEEDED: number of 18x18 multipliers] | [DATA_NEEDED: number of DSP blocks and precision] |
| PLLs | [DATA_NEEDED: total PLL count] | — |
| Core Voltage | 1.1 V | — |
| Process Technology | TSMC 65 nm | 40 nm CMOS |
| Packhaging | 1517-BBGA, FCBGA | 780-BBGA, FCBGA (H780) |
| Package Body Size | [DATA_NEEDED: mm x mm] | — |
| Temperature na Operasyon | -40 °C to +100 °C (Industrial) | 0 °C to +85 °C (C grade, commercial) |
| Operating Temperature Grade | Industrial (I4) | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Lead-Free / RoHS | [DATA_NEEDED: explicit RoHS statement] | — |
| Level ng MSL | [DATA_NEEDED: MSL classification] | — |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| User I/Os | — | 488 |
| Number of Pins / Balls | — | 780 |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Tindminan RoHS | — | Compliant (lead-free 'N' suffix) |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |