EP3SE260H780C4 vs EP3SE260H780C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SE260H780C4 sa pamamagitan ng Intel at EP3SE260H780C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP3SE260H780C4 - Stratix III E FPGA, 255K LE, 780-FCBGA | Intel / Altera
EP3SE260H780C4 ObsoleteIntel
EP3SE260H780C3N - Stratix III E FPGA, 255K LE, 780-BGA | Intel / Altera
EP3SE260H780C3N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EP3SE260H780C4 | EP3SE260H780C3N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Aktibo |
| Family | Stratix III E | — |
| Logic Elements | 255,000 | — |
| Total Memory Bits | 16,672,640 bits | — |
| Logic Array Blocks (LABs) | 10,200 | — |
| User I/Os | 488 | 488 |
| Embedded Multipliers (18x18) | 576 | — |
| Distributed Memory | 1,020 Kbits | — |
| Number of PLLs | 8 | — |
| Core Voltage | 0.9 V | — |
| Auxiliary Voltage | 1.1 V | — |
| Process Technology | 65 nm | 40 nm CMOS |
| Speed Grade | C4 | — |
| Packhaging | 780-ball FCBGA (H780) | 780-BBGA, FCBGA (H780) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | Compliant | Compliant (lead-free 'N' suffix) |
| Series | — | Stratix® III E |
| Logic Elements (LE) | — | 255,000 |
| Embedded Memory (bits) | — | 16,672,768 |
| Number of LABs/CLBs | — | 10,200 |
| Number of Pins / Balls | — | 780 |
| Temperature na Operasyon | — | 0 °C to +85 °C (C grade, commercial) |
| Maximum Core Frequency | — | [DATA_NEEDED: maximum core frequency MHz] |
| Supply Voltage (VCCINT) | — | [DATA_NEEDED: VCCINT nominal V] |
| Transceivers | — | [DATA_NEEDED: number of embedded transceivers and max data rate] |
| DSP Blocks | — | [DATA_NEEDED: number of DSP blocks and precision] |
| Level ng Sensitivity sa Asid ng Moisture (MSL) | — | [DATA_NEEDED: MSL level per JEDEC J-STD-020] |
| Configuration Method | — | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel |
| Design Toolchain | — | Altera Quartus II (legacy); Intel Quartus Prime |