EP3SL200H780I4LN vs EP3SL200H780C3N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP3SL200H780I4LN sa pamamagitan ng Altera at EP3SL200H780C3N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP3SL200H780I4LN | EP3SL200H780C3N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Series | Stratix III L | — |
| Family | Stratix III L (Low-Power) | Stratix III L (low-power) |
| Manufacturer | Intel / Altera (now Intel PSG) | — |
| Number of Logic Elements / Cells | 200,000 | — |
| Number of LABs / CLBs | 8,000 | — |
| Total RAM Bits | 10,901,504 (approximately 10.9 Mbit) | — |
| Number of I/O | 488 | — |
| Voltage - Supply | 0.9 V core (selectable Vcore) | — |
| Temperature na Operasyon | -40C to +100C (industrial) | 0C to +85C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Packhaging / Kaso | 780-BBGA, FCBGA (Flip-Chip BGA) | — |
| Process Technology | 65 nm CMOS | — |
| Speed Grade | I4 (Industrial, mid-speed grade) | C3 (commercial, -3 speed) |
| Tindminan RoHS | RoHS Compliant (lead-free) | — |
| Level ng MSL | MSL 3 (168 Hours, per JEDEC J-STD-020) | 3 |
| Roaming Pin Name Suffix | LN = lead-free, industrial temp, H780 780-ball package | — |
| Process Node | — | 40 nm |
| Logic Elements | — | 200,000 |
| Embedded Memory Bits | — | 10,901,504 bits |
| Logic Array Blocks (LABs) | — | 8,000 |
| User I/Os | — | 488 |
| Packhaging | — | 780-Ball FCBGA (HBGA), 29 x 29 mm |
| Maximum Internal Clock Frequency | — | 800 MHz |
| Transceivers | — | 24 channels, up to 3.75 Gbps |
| DSP Blocks | — | 384 |
| Voltage - Core | — | 0.9 V / 1.0 V (core, VCC) |
| Voltage - I/O | — | 1.2 V to 3.3 V (VCCIO banks) |
| Lead-Free / RoHS | — | Yes |
| Mounting Pitch | — | 1.0 mm ball pitch |
| PLLs | — | 12 (Stratix III PLL array) |
| Configuration | — | JTAG IEEE Std 1149.1, passive/active serial |