EP610DC-10 vs EP610PC-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-10 sa pamamagitan ng Intel at EP610PC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610DC-10 EP610PC-15
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Device Family Altera Classic EPLD —
Macrocells 16 16
Maximum Pipelined Data Rate 100 MHz —
Pin-to-Pin Propagation Delay (tpd) 10 ns —
Speed Grade -10 —
Packhaging 24-pin CDIP (Ceramic DIP, windowed) PDIP-24 (plastic DIP, 24-pin)
Uri ng Pagpapasok Through-Hole Through-Hole (DIP)
Technology CMOS, EPROM-based (UV-erasable) CMOS
Volte ng Pagbibigay 5 V (single supply) —
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: operating temperature range]
I/O Pins [DATA_NEEDED: exact I/O count for CDIP-24 variant] —
Logic Elements 16 macrocells (programmable AND/OR array) —
Configuration Memory UV-erasable EPROM —
Reprogrammable Yes (UV erase window on package) —
Tindminan RoHS [DATA_NEEDED: not stated in verified web data] [DATA_NEEDED: RoHS status]
Family — Classic EPLD
Device Type — EPLD (Erasable Programmable Logic Device)
Usable Gates — 300 gates
Logic Delay (tPD) — 15 ns (pin-to-pin, -15 speed grade)
Maximum Counter Frequency — 100 MHz (per family datasheet)
Pipelined Data Rate — Up to 100 MHz
Supply Voltage (VCC) — 5 V (single supply)
Architecture — PAL-type, sum-of-products AND/OR array
TTL Emulation — 100% TTL compatible
Bilang ng Pin — 24 pins
Development Tool — Altera MAX+PLUS II
Logic Test Circuitry — On-board for AC/DC verification

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