EP610DC-35 vs EP610DM-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC-35 sa pamamagitan ng Altera at EP610DM-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC-35 | EP610DM-35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Device Type | CPLD - Classic EPLD | — |
| Family | Altera Classic EP610 | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| Process Technology | CMOS | — |
| Program/erase Method | UV-erasable (windowed CERDIP) | — |
| Packhaging | 24-pin CDIP (windowed CERDIP) 0.300 inch | 24-pin CDIP (CERDIP) with UV window |
| Uri ng Pagpapasok | Through-Hole (DIP) | — |
| Temperature na Operasyon | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] | — |
| Manufacturer | Originally Altera; today supplied via Rochester Electronics (authorized) | Altera (Rochester Electronics authorized stock) |
| Tindminan RoHS | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] | Non-compliant (contains lead, hermetic CERDIP) |
| Part Family | — | Classic EPLD |
| Logic Family | — | PAL-type EPLD, CMOS, UV-erasable |
| Number of Macrocells | — | 16 |
| Number of Gates | — | 300 |
| Pipelined Data Rate (fMAX) | — | 100 MHz |
| Temperature Grade (M) | — | Military -55°C to +125°C |
| I/O Pins | — | 24 dedicated I/O (input + bidirectional) |
| Programmability | — | UV-erasable, reprogrammable |
| Hanay ng Temperature na Operasyon | — | -55°C to +125°C |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |