EP610DC15 vs EP610DC35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC15 sa pamamagitan ng Intel at EP610DC35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC15 | EP610DC35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | — |
| Family | EP610 Classic EPLD | Classic EPLD |
| Macrocells | 16 | — |
| Architecture | PAL-type | — |
| Propagation Delay (tPD) | 15 ns | 35 ns |
| Maximum Clock Frequency (fMAX) | 71.4 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Total Inputs | 20 | — |
| I/O Lines | 16 | — |
| Product Terms | 160 | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Technology | CMOS | UV-erasable CMOS EPROM |
| Temperature na Operasyon | 0C to +70C | [DATA_NEEDED: operating temperature range] |
| Packhaging | 24-pin CDIP (Ceramic DIP, windowed) | 24-pin CDIP (Ceramic DIP) with quartz erase window |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Reprogrammability | Yes (UV erasable via windowed package) | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 16 macrocells |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 28.6 MHz |
| Volte ng Pagbibigay | — | 5 V |
| Bilang ng Pin | — | 24 |
| Programming Method | — | Altera legacy programmer (PLDLMax or compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| I/O Pins | — | [DATA_NEEDED: number of user I/O pins] |