EP610DC35 vs EP610DC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DC35 sa pamamagitan ng Altera at EP610DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610DC35 | EP610DC-35 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Classic EPLD | Altera Classic EP610 |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 35 ns | 35 ns |
| Maximum Frequency | 28.6 MHz | — |
| Pipelined Data Rate | up to 100 MHz | up to 100 MHz |
| Volte ng Pagbibigay | 5 V | — |
| Packhaging | 24-pin CDIP (Ceramic DIP) with quartz erase window | 24-pin CDIP (windowed CERDIP) 0.300 inch |
| Uri ng Pagpapasok | Through-Hole | Through-Hole (DIP) |
| Bilang ng Pin | 24 | — |
| Technology | UV-erasable CMOS EPROM | — |
| Programming Method | Altera legacy programmer (PLDLMax or compatible) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) [DATA_NEEDED: explicit range from datasheet] |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not explicitly confirmed in retrieved data; CERDIP packages typically non-RoHS] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Pins | [DATA_NEEDED: number of user I/O pins] | — |
| Device Type | — | CPLD - Classic EPLD |
| Macrocells | — | 16 |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Supply Voltage (VCC) | — | 5 V |
| Process Technology | — | CMOS |
| Program/erase Method | — | UV-erasable (windowed CERDIP) |
| Manufacturer | — | Originally Altera; today supplied via Rochester Electronics (authorized) |