EP610DI-35 vs EP610DC35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610DI-35 sa pamamagitan ng Intel at EP610DC35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 ObsoletePagsanggunian na paghahambing
| Parametro | EP610DI-35 | EP610DC35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD |
| Series | EP610 | — |
| Logic Cells / Macrocells | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Product Terms | 160 | — |
| I/O Pins | 16 bidirectional | [DATA_NEEDED: number of user I/O pins] |
| Total Inputs | 20 (including 4 dedicated inputs) | — |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Internal Pipelined Data Rate | Up to 100 MHz | — |
| Volte ng Pagbibigay | 5 V | 5 V |
| Technology | CMOS, UV-erasable | UV-erasable CMOS EPROM |
| Packhaging | 24-pin CDIP (Ceramic DIP) | 24-pin CDIP (Ceramic DIP) with quartz erase window |
| Uri ng Pagpapasok | Through-hole | Through-Hole |
| Temperature na Operasyon | [DATA_NEEDED: industrial/commercial grade range] | [DATA_NEEDED: operating temperature range] |
| Tindminan RoHS | [DATA_NEEDED: not confirmed in supplied web data] | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 16 macrocells |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| Bilang ng Pin | — | 24 |
| Programming Method | — | Altera legacy programmer (PLDLMax or compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |