EP610DI-35 vs EP610DC35 比較
詳細並排比較 EP610DI-35 由 Intel 與 EP610DC35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 Obsolete規格比較
| 參數 | EP610DI-35 | EP610DC35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD |
| Series | EP610 | — |
| Logic Cells / Macrocells | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Product Terms | 160 | — |
| I/O Pins | 16 bidirectional | [DATA_NEEDED: number of user I/O pins] |
| Total Inputs | 20 (including 4 dedicated inputs) | — |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Internal Pipelined Data Rate | Up to 100 MHz | — |
| 供應電壓 | 5 V | 5 V |
| Technology | CMOS, UV-erasable | UV-erasable CMOS EPROM |
| 封裝 | 24-pin CDIP (Ceramic DIP) | 24-pin CDIP (Ceramic DIP) with quartz erase window |
| 安裝類型 | Through-hole | Through-Hole |
| 工作溫度 | [DATA_NEEDED: industrial/commercial grade range] | [DATA_NEEDED: operating temperature range] |
| RoHS 狀態 | [DATA_NEEDED: not confirmed in supplied web data] | [DATA_NEEDED: RoHS status] |
| Logic Elements | — | 16 macrocells |
| Propagation Delay (tPD) | — | 35 ns |
| Maximum Frequency | — | 28.6 MHz |
| Pipelined Data Rate | — | up to 100 MHz |
| 腳位數 | — | 24 |
| Programming Method | — | Altera legacy programmer (PLDLMax or compatible) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |