EP610ILC-10 vs EP610DC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610ILC-10 sa pamamagitan ng Altera at EP610DC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610ILC-10 | EP610DC-30 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | Classic EPLD (Erasable Programmable Logic Device) |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Product Terms | 160 | — |
| I/O Pins | 16 | 16 (with output enable) |
| Dedicated Inputs | 4 | 16 |
| Volte ng Pagbibigay | 5 V (single supply) | — |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Packhaging | PLCC-28 (plastic J-lead chip carrier) | 24-pin CERDIP (windowed) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket or solder) | Through-Hole |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | Commercial (0C to +70C) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | — |
| Family | — | EP610 (Classic Device Family) |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 30 ns |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |