EP610LC-35 vs EP610LC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610LC-35 sa pamamagitan ng Altera at EP610LC-30 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610LC-35 | EP610LC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD (EP610) |
| Device Series | EP610 | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tpd) | 37 ns | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EEPROM (one-time-programmable plastic) | CMOS EPROM (UV-erasable) |
| Packhaging | 28-pin PLCC (J-lead) | 24-pin CERDIP / PDIP |
| Temperature na Operasyon | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| Speed Grade | -35 (slowest EP610) | — |
| Uri ng Pagpapasok | Surface Mount | Through-Hole |
| Programmable Pins | 24 input / 16 output (shared macrocells) | — |
| Tindminan RoHS | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead_free] | — |
| Level ng MSL | [DATA_NEEDED: msl_level] | — |
| Programming Tool | MAX+PLUS II development system | — |
| Macro Cells | — | 16 |
| Logic Gates | — | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | — | 13 V nominal |
| Erase/Program Cycles | — | 1000 typical |
| Type ng Output | — | CMOS tri-state (programmable) |
| Logic Compatibility | — | TTL and CMOS |
| Turbo Mode | — | Yes (registered path bypass) |