EP610LC-35 vs EP610LC-30 比較
詳細並排比較 EP610LC-35 由 Altera 與 EP610LC-30 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610LC-35 | EP610LC-30 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD (EP610) |
| Device Series | EP610 | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Propagation Delay (tpd) | 37 ns | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EEPROM (one-time-programmable plastic) | CMOS EPROM (UV-erasable) |
| 封裝 | 28-pin PLCC (J-lead) | 24-pin CERDIP / PDIP |
| 工作溫度 | Commercial (0C to +70C) [DATA_NEEDED: exact grade letter] | 0 C to +70 C (commercial) / -55 C to +125 C (military) |
| Speed Grade | -35 (slowest EP610) | — |
| 安裝類型 | Surface Mount | Through-Hole |
| Programmable Pins | 24 input / 16 output (shared macrocells) | — |
| RoHS 狀態 | [DATA_NEEDED: rohs_status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead_free] | — |
| MSL 等級 | [DATA_NEEDED: msl_level] | — |
| Programming Tool | MAX+PLUS II development system | — |
| Macro Cells | — | 16 |
| Logic Gates | — | Equivalent to 300 gates (typical) |
| Pin-to-Pin Delay (tPD) | — | 30 ns |
| Pipelined Data Rate | — | up to 100 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Programming Voltage (VPP) | — | 13 V nominal |
| Erase/Program Cycles | — | 1000 typical |
| 輸出類型 | — | CMOS tri-state (programmable) |
| Logic Compatibility | — | TTL and CMOS |
| Turbo Mode | — | Yes (registered path bypass) |