EP910DM-40 vs EP910ILC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DM-40 sa pamamagitan ng Altera at EP910ILC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910DM-40 | EP910ILC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | EP910 Classic EPLD |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 36 | — |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 25 ns |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| Packhaging | 40-pin Ceramic DIP (Cerdip) with UV window | 44-pin JLCC (windowed ceramic) |
| Uri ng Pagpapasok | Through-Hole (DIP) | Surface Mount |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial) |
| Volte ng Pagbibigay | 5 V | 5 V |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | non_compliant (ceramic windowed package) |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| User I/O Pins | — | 36 |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Technology | — | CMOS EPROM (UV-erasable) |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Katayuan ng Lifecycle | — | Obsolete - last time buy was late 1990s |