EP910DM-40 vs EP910LC-35H Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910DM-40 sa pamamagitan ng Altera at EP910LC-35H sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910DM-40 EP910LC-35H
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type UV Erasable Programmable Logic Device (EPLD) —
Family Altera Classic EP910 Classic EPLD (EP910)
Architecture PAL-type AND/OR with global programmable interconnect bus —
Macrocells 24 —
Dedicated Inputs 36 10
Dedicated Outputs 24 —
Bidirectional I/O Lines 24 —
Product Terms 240 —
Propagation Delay (tPD) 40 ns —
External Clocks 2 —
Process Technology CMOS —
Packhaging 40-pin Ceramic DIP (Cerdip) with UV window 40-pin Ceramic DIP (H suffix)
Uri ng Pagpapasok Through-Hole (DIP) Through-hole (Ceramic DIP)
Temperature na Operasyon [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature range grade]
Volte ng Pagbibigay 5 V —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] unknown
Programming Interface JEDEC-standard fuse-map / UV erasure —
Logic Elements — 24 macrocells
Equivalent Gates — 450 usable gates
Propagation Delay (tpd) — 35 ns
Supply Voltage (VCC) — 5 V (4.75 V to 5.25 V)
Technology — CMOS, UV-erasable EPROM
User I/O Pins — 36
Erasure Method — UV (quartz window on H package)
Programming Method — Altera hardware programmer
Logic Levels — TTL compatible
Kuru-kuryente ng Kapayapaan — [DATA_NEEDED: typical ICC value]
Process Node — [DATA_NEEDED: process geometry]
Lifecycle — Obsolete (long-term supply via Rochester Electronics)

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