EP910DM-40 vs EP910LC-35H 比較
詳細並排比較 EP910DM-40 由 Altera 與 EP910LC-35H 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910DM-40 | EP910LC-35H |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | UV Erasable Programmable Logic Device (EPLD) | — |
| Family | Altera Classic EP910 | Classic EPLD (EP910) |
| Architecture | PAL-type AND/OR with global programmable interconnect bus | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 36 | 10 |
| Dedicated Outputs | 24 | — |
| Bidirectional I/O Lines | 24 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | — |
| External Clocks | 2 | — |
| Process Technology | CMOS | — |
| 封裝 | 40-pin Ceramic DIP (Cerdip) with UV window | 40-pin Ceramic DIP (H suffix) |
| 安裝類型 | Through-Hole (DIP) | Through-hole (Ceramic DIP) |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range grade] |
| 供應電壓 | 5 V | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | unknown |
| Programming Interface | JEDEC-standard fuse-map / UV erasure | — |
| Logic Elements | — | 24 macrocells |
| Equivalent Gates | — | 450 usable gates |
| Propagation Delay (tpd) | — | 35 ns |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Technology | — | CMOS, UV-erasable EPROM |
| User I/O Pins | — | 36 |
| Erasure Method | — | UV (quartz window on H package) |
| Programming Method | — | Altera hardware programmer |
| Logic Levels | — | TTL compatible |
| 靜態電流 | — | [DATA_NEEDED: typical ICC value] |
| Process Node | — | [DATA_NEEDED: process geometry] |
| Lifecycle | — | Obsolete (long-term supply via Rochester Electronics) |