EP910IPC-15 vs EP910DC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910IPC-15 sa pamamagitan ng Altera at EP910DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910IPC-15 EP910DC-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family Altera Classic EPLD (EP910 series) —
Product Type Erasable Programmable Logic Device (EPLD) —
Architecture PAL-type, CMOS PAL-type sum-of-products AND-OR array
Macrocells 24 24
Dedicated Inputs 12 12
I/O Pins 24 24
Product Terms 240 240
External Clocks 2 —
Propagation Delay (tPD) 15 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V —
Temperature na Operasyon 0C to +70C (commercial, IPC suffix) 0 °C to +70 °C (commercial)
Packhaging PDIP-40 (Plastic DIP, 40-pin) 40-pin CDIP (Ceramic DIP) with quartz window
Uri ng Pagpapasok Through-Hole —
Process Technology CMOS —
Programming Method JEDEC fuse map via Altera EPLD programmer JEDEC fuse map via device programmer; UV erase
Bilang ng Pin 40 —
Tindminan RoHS [DATA_NEEDED: rohs status not confirmed in verified data] Non-compliant (ceramic DIP with Pb-bearing lead finish)
Device Type — UV-Erasable CMOS PLD (PAL-type)
Family — Classic EPLD EP910
Usable Gates — 900 gates
Total Inputs — 36
Propagation Delay (tpd) — 35 ns
Maksimum na Taktiko ng Oras — 37 MHz (typical, internal)
Supply Voltage (Vcc) — 4.75 V to 5.25 V (5 V nominal)
Lead Pitch — 2.540 mm
Termination Style — Through-Hole
Technology — CMOS, UV-erasable EPROM cell
Lifecycle — Obsolete / last-time-buy from authorized distributors

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