EP910LC-40H vs EP910DC-40 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-40H sa pamamagitan ng Altera at EP910DC-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910LC-40H EP910DC-40
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Classic EPLD (EP910) —
Macro Cells 24 —
Usable Gates 450 —
Logic Elements 24 macro cells / expandable to 48 via expander terms —
Propagation Delay (tPD) 40 ns max —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Supply Current (ICC) Low-power CMOS, typical ICC < 100 mA —
Technology CMOS, UV-erasable EPROM —
Packhaging 40-pin Ceramic DIP (CDIP-40), JEDEC standard DIP-40 (ceramic, through-hole)
Uri ng Pagpapasok Through-Hole (THT) Through-Hole
Temperature na Operasyon -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] —
Speed Grade -40 (40 ns tPD) —
Programming Method UV-erase + EPROM program, ~100 erase cycles UV-erase + EPROM programmer; on-board logic test circuitry
I/O Pins [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] —
Tindminan RoHS [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] [DATA_NEEDED: rohs_status]
Device Family — Classic EPLD (EP910 series)
Architecture — PAL-type AND/OR, UV-erasable CMOS
Macrocells — 24
Dedicated Inputs — 12
Bidirectional I/O Pins — 24
Total Inputs to Logic Array — 36
Product Terms — 240 maximum
Maximum Propagation Delay (tPD) — 40 ns
Maximum Operating Frequency (fMAX) — 25 MHz
Global Clocks — 2
Volte ng Pagbibigay — 5 V (typical for Classic EPLD family)
Operating Temperature (Commercial) — 0 °C to 70 °C

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita