EP910LC-40H vs EP910DC-40 Karşılaştırma

Ayrıntılı yan yana karşılaştırma EP910LC-40H tarafından Altera ve EP910DC-40 tarafından AlteraAnahtar özellikleri, elektriksel parametreleri, ambalajı, yaşam döngüsü durumu, fiyatlandırma ve mevcudiyeti karşılaştırarak tasarım gereksinimleriniz için en iyi bileşeni belirleyin.

Özellik Karşılaştırması

Parametre EP910LC-40H EP910DC-40
Marka Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Yaşam Döngüsü Durumu Obsolete Obsolete
Family Classic EPLD (EP910) —
Macro Cells 24 —
Usable Gates 450 —
Logic Elements 24 macro cells / expandable to 48 via expander terms —
Propagation Delay (tPD) 40 ns max —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) —
Supply Current (ICC) Low-power CMOS, typical ICC < 100 mA —
Technology CMOS, UV-erasable EPROM —
Paket 40-pin Ceramic DIP (CDIP-40), JEDEC standard DIP-40 (ceramic, through-hole)
Montaj Türü Through-Hole (THT) Through-Hole
İşletim Sıcaklığı -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] —
Speed Grade -40 (40 ns tPD) —
Programming Method UV-erase + EPROM program, ~100 erase cycles UV-erase + EPROM programmer; on-board logic test circuitry
I/O Pins [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] —
RoHS Durumu [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] [DATA_NEEDED: rohs_status]
Device Family — Classic EPLD (EP910 series)
Architecture — PAL-type AND/OR, UV-erasable CMOS
Macrocells — 24
Dedicated Inputs — 12
Bidirectional I/O Pins — 24
Total Inputs to Logic Array — 36
Product Terms — 240 maximum
Maximum Propagation Delay (tPD) — 40 ns
Maximum Operating Frequency (fMAX) — 25 MHz
Global Clocks — 2
Besleme Gerilimi — 5 V (typical for Classic EPLD family)
Operating Temperature (Commercial) — 0 °C to 70 °C

Dökümanlar & Kaynaklar

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