EPC8QI100N vs EPC8QC100DM Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC8QI100N sa pamamagitan ng Altera at EPC8QC100DM sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC8QI100N EPC8QC100DM
Brand Altera Intel
Kategorya EEPROM EEPROM
Katayuan ng Lifecycle NRND Obsolete
Manufacturer Altera (Intel) —
Part Family EPC8 (Enhanced Configuration) —
Device Type Configuration PROM for SRAM-based FPGAs —
Laki ng Memory 8 Mbit (8,388,608 bits) 8 Mb (1 MB)
Programmable Type In System Programmable (Flash) —
Configuration Interface Altera serial (4-wire: DATA, DCLK, nCS, nINIT_CONF) —
Maximum Configuration Clock 50 MHz —
On-Chip Decompression Yes (Altera compression algorithm) —
Supply Voltage (VCC) 3.0 V to 3.6 V 3.0 V to 3.6 V (3.3 V typical)
Temperature na Operasyon -40 °C to +85 °C (Industrial) -40 C to +85 C (industrial / DM suffix)
Packhaging 100-PQFP / 100-BQFP (20 x 14 mm) 100-PQFP (20 x 14 mm)
Bilang ng Pin 100 —
Uri ng Pagpapasok Surface Mount Surface Mount
Lead-Free / RoHS Yes (per distributor listings) —
JTAG (IEEE 1149.1) ISP Supported —
Multi-Device Daisy-Chain Supported —
Target FPGA Families ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX —
Packaging Tray —
Uri ng Memory — Non-volatile configuration PROM
Interface — Serial (Passive Serial / Passive Parallel Synchronous / Active Serial)
Maximum DCLK Frequency — 40 MHz
In-System Programming — Yes (IEEE 1149.1 / IEEE 1532 JTAG)
Cascade Support — Yes - two EPC8 devices for 16 Mb
Level ng MSL — 1 (Unlimited)
Tindminan RoHS — Compliant
Lead-Free / Halogen-Free — Lead-free (per supplier); halogen status not in datasheet excerpt
Compatible FPGA Families — Cyclone, Cyclone II, Cyclone III, Stratix, Arria
Configuration Modes — PS, PPS, AS (with appropriate FPGA master)
Programming Cycles — [DATA_NEEDED: minimum erase/write endurance cycles]

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