EPF6016QC208-3N vs EPF6016QC208 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPF6016QC208-3N sa pamamagitan ng Altera at EPF6016QC208 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPF6016QC208-3N EPF6016QC208
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family FLEX 6000 FLEX 6000
Logic Elements / Cells 1,320 cells —
Usable Gates 16,000 gates —
Logic Array Blocks (LABs) 132 132 LABs (10 LEs per LAB)
Maximum User I/O 171 171 I/O pins
Maximum Operating Frequency 125 MHz (internal, per family spec) —
Internal Toggle Rate Up to 172 MHz —
Process Technology 0.42 µm CMOS, SRAM-based 0.42 um CMOS (SRAM-based)
Core Supply Voltage (VCCINT) 5.0 V —
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V —
Packhaging 208-pin PQFP (Power Quad Flat Pack) PQFP-208 (Plastic Quad Flat Pack)
Uri ng Pagpapasok Surface Mount Surface Mount
Configuration Method Serial configuration EPROM or JTAG (ByteBlaster) —
Temperature na Operasyon 0 °C to +85 °C (commercial) 0C to 70C (commercial)
Tindminan RoHS unknown Non-compliant (legacy 5V PQFP, contains lead)
Lifecycle Obsolete (Altera FLEX 6000 family EOL) —
Equivalent Gates — 16,000 gates
Logic Cells / Logic Elements (LEs) — 1,320 LEs
Maximum Internal Frequency — 125 MHz
Supply Voltage (VCCINT) — 5.0 V
I/O Standard Support — 5.0 V CMOS (3.3 V VCCIO supported)
Configuration Memory — SRAM (volatile, requires external config EPROM)
Bilang ng Pin — 208 pins
JTAG Support — IEEE Std 1149.1 boundary scan
Configuration Device Compatibility — EPC1, EPC2 (legacy Altera config PROMs)

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