EPM3128ATC100-5 vs EPM3128ATC144-5 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATC100-5 sa pamamagitan ng Intel at EPM3128ATC144-5 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3128ATC100-5 | EPM3128ATC144-5 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Series | MAX 3000A | — |
| Family | CPLD - MAX 3000A | MAX 3000A |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | — |
| User I/Os | 80 | — |
| Dedicated Inputs | 4 | — |
| Pin-to-Pin Delay (tpd) | 5 ns (commercial); 7.5 ns | — |
| Maximum Frequency (fCNT) | 192.3 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 3.3 V | — |
| Output Drive Voltage | 2.5 V or 3.3 V (programmable) | — |
| Input Tolerance | 2.5 V, 3.3 V, 5.0 V tolerant | — |
| Program Memory Type | EEPROM | EEPROM (non-volatile) |
| In-System Programmability | Yes, IEEE Std. 1532 compliant | Yes (IEEE Std. 1532 compliant) |
| JTAG Boundary Scan | Yes, IEEE Std. 1149.1 | — |
| Temperature na Operasyon | 0 °C to 70 °C (Commercial) | 0C to +70C (Commercial) |
| Packhaging | 100-pin TQFP (Fine Line) | TQFP-144 (Plastic, 1.0 mm pitch, 22x22 mm) |
| Uri ng Pagpapasok | Surface Mount | — |
| Logic Family | CMOS | CMOS |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Not Compliant (per Arrow distributor listing) |
| Process Technology | CMOS EEPROM | 0.30 um CMOS EEPROM, 4 metal layers |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | — | 128 |
| Number of Logic Array Blocks (LABs) | — | 8 |
| Number of User I/Os | — | 96 |
| Device System Gates | — | 2500 |
| Product Terms per Macrocell | — | 32 |
| Propagation Delay (tPD) | — | 7.5 ns |
| Maximum Internal Frequency | — | 192.3 MHz |
| Number of Global Clocks | — | 2 |
| Supply Voltage (Core) | — | 3.3 V |
| Multi-Volt I/O Voltage | — | 2.5 V / 3.3 V / 5.0 V tolerant |
| JTAG / IEEE 1149.1 | — | Yes (boundary-scan + ISP) |
| ECCN | — | EAR99 |
| HTS Code | — | 8542.31.00.55 |