EPM3128ATC144-7N vs EPM3128ATI144-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3128ATC144-7N sa pamamagitan ng Altera at EPM3128ATI144-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3128ATC144-7N - MAX 3000A CPLD, 128 Macrocells, 7.5ns | Altera
EPM3128ATC144-7N ✓ NakahandaAltera
EPM3128ATI144-10 - MAX 3000A CPLD 128 Macro 98 I/O TQFP-144 | Intel/Altera
EPM3128ATI144-10 NrndPagsanggunian na paghahambing
| Parametro | EPM3128ATC144-7N | EPM3128ATI144-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Presyo ng Yunit (USD) | $9.25 | — |
| Series | MAX 3000A | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | EEPROM-based, MAX architecture | — |
| Number of Macrocells | 128 | — |
| Number of Usable Gates | Up to 10,000 | — |
| User I/Os | 96 | 98 |
| Bilang ng Pin | 144 | 144 |
| Packhaging | TQFP-144 (20 x 20 mm, 0.5 mm pitch) | TQFP-144 (FINE LINE) |
| Logic Family | CMOS | CMOS, EEPROM-based |
| Propagation Delay (tPD) | 7.5 ns (pin-to-pin, -7 speed grade) | — |
| Counter Frequency | Up to 227.3 MHz | 98 MHz typical |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | -40C to +85C (Industrial) |
| In-System Programmability (ISP) | Yes, via JTAG (IEEE 1149.1) | — |
| PCI Compliance | Compatible with PCI Local Bus Specification Rev. 2.2 | PCI Local Bus Spec Rev 2.2 (speed grades -4 to -10) |
| Uri ng Pagpapasok | Surface Mount (SMD/SMT) | Surface Mount (Gull-Wing TQFP) |
| Tindminan RoHS | Lead-free (-7N suffix indicates Pb-free finish) | Compliant (lead-free TQFP) |
| Family | — | MAX 3000A |
| Usable Gates | — | 2,500 |
| Macro Cells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Supply Voltage (VCCINT) | — | 3.3 V |
| Pin-to-Pin Delay | — | 10 ns (speed grade -10) |
| Programming Interface | — | IEEE 1149.1 JTAG (ISP) |