EPM3512AFI256-10 vs EPM3512AFC256-7N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFI256-10 sa pamamagitan ng Intel at EPM3512AFC256-7N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFI256-10 EPM3512AFC256-7N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Aktibo Obsolete
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Equivalent Gates 10,000 —
Macrocells 512 512
User I/Os 208 208
Pin-to-Pin Logic Delay (tPD) 4.5 ns —
Maximum Counter Frequency 227.3 MHz —
Propagation Delay 7.5 ns (max, per chipdig summary) —
Core Voltage 3.3 V —
MultiVolt I/O Levels 5.0 V / 3.3 V / 2.5 V —
Process Technology CMOS EEPROM CMOS EEPROM, 0.30 um
In-System Programmability Yes, IEEE Std. 1532 (3.3 V ISP) IEEE Std. 1532 compliant
Packhaging FBGA-256 (FineLine BGA, 256 balls) 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch
Temperature na Operasyon 0C to +70C (commercial) 0 C to 70 C (commercial)
Logic Family CMOS —
Tindminan RoHS [DATA_NEEDED: rohs_status] [DATA_NEEDED: RoHS status]
Volte ng Pagbibigay 3.3 V (core); MultiVolt I/O to 5.0 V —
Usable Gates — 10,000
Logic Blocks — 16 (32 macrocells each)
Propagation Delay (tPD) — 7.5 ns
Maximum Internal Frequency (fMAX) — 116.3 MHz
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
5V Tolerant I/O — Yes
Programming Interface — JTAG (IEEE 1149.1)
Uri ng Pagpapasok — Surface Mount

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