EPM3512AQC210-10 vs EPM3256AQC208-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC210-10 sa pamamagitan ng Altera at EPM3256AQC208-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AQC210-10 EPM3256AQC208-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Logic Macrocells 512 —
Logic Array Blocks (LABs) 16 (32 macrocells each) —
Maximum User I/O Pins 172 —
Speed Grade -10 (10 ns tPD) —
Pin-to-Pin Propagation Delay (tPD1, max) 10 ns —
Maximum Operating Frequency (fCNT) 125 MHz —
Supply Voltage - Core (VCCINT) 3.3 V —
Supply Voltage - I/O (VCCIO) 3.3 V or 2.5 V —
Input Voltage Tolerance 5.0 V tolerant —
Programmable Technology EEPROM (in-system programmable) —
Programming Interface JTAG (IEEE 1149.1) / ISP IEEE 1149.1 JTAG (ISP)
Packhaging PQFP-210 208-BFQFP (PQFP, Gull Wing)
Temperature na Operasyon 0C to +70C (commercial) 0 °C to +70 °C (Commercial)
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: rohs_compliance_status] [DATA_NEEDED: RoHS status]
Logic Family — CMOS (EEPROM-based)
Macrocells — 256
Usable Gates — 5,000
User I/Os — 161
Bilang ng Pins — 208
Pin-to-Pin Propagation Delay — 10 ns
Counter Frequency (max) — 227.3 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Tolerance — MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant
PCI-SIG Compliance — Yes (speed grades -4, -5, -6, -7, -10)
Global Clock Networks — 4 (CLK, CLR, OE, GCLK)

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