EPM3512AQC210-10 vs EPM3256AQC208-10 比較

詳細並排比較 EPM3512AQC210-10 由 Altera 與 EPM3256AQC208-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPM3512AQC210-10 EPM3256AQC208-10
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Logic Macrocells 512 —
Logic Array Blocks (LABs) 16 (32 macrocells each) —
Maximum User I/O Pins 172 —
Speed Grade -10 (10 ns tPD) —
Pin-to-Pin Propagation Delay (tPD1, max) 10 ns —
Maximum Operating Frequency (fCNT) 125 MHz —
Supply Voltage - Core (VCCINT) 3.3 V —
Supply Voltage - I/O (VCCIO) 3.3 V or 2.5 V —
Input Voltage Tolerance 5.0 V tolerant —
Programmable Technology EEPROM (in-system programmable) —
Programming Interface JTAG (IEEE 1149.1) / ISP IEEE 1149.1 JTAG (ISP)
封裝 PQFP-210 208-BFQFP (PQFP, Gull Wing)
工作溫度 0C to +70C (commercial) 0 °C to +70 °C (Commercial)
安裝類型 Surface Mount Surface Mount
RoHS 狀態 [DATA_NEEDED: rohs_compliance_status] [DATA_NEEDED: RoHS status]
Logic Family — CMOS (EEPROM-based)
Macrocells — 256
Usable Gates — 5,000
User I/Os — 161
腳位數 — 208
Pin-to-Pin Propagation Delay — 10 ns
Counter Frequency (max) — 227.3 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Tolerance — MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant
PCI-SIG Compliance — Yes (speed grades -4, -5, -6, -7, -10)
Global Clock Networks — 4 (CLK, CLR, OE, GCLK)

資料表與資源

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