EPM5032DC20 vs EPM5032DM883B Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DC20 sa pamamagitan ng Altera at EPM5032DM883B sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032DC20 | EPM5032DM883B |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable PLD (CPLD class) | — |
| Macrocells | 32 | 32 |
| Usable Gates | 600 | — |
| Propagation Delay (tPD) | 20 ns | [DATA_NEEDED: tPD in ns] |
| Maximum Frequency (Fmax) | 71.4 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V (nominal, TTL-compatible I/O) |
| Dedicated Inputs | 7 | — |
| I/O Pins | 16 (bidirectional) | — |
| Total Inputs (max) | 24 | — |
| Output Macrocells | 16 | — |
| Clock Inputs | 1 (global) | — |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS | — |
| Packhaging | 20-pin Ceramic DIP (DC) with UV window | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | MILITARY (per /883B screen) |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: lead-bearing ceramic; likely non-compliant] |
| Family | — | MAX 5000 (Classic EPLD) |
| Logic Elements | — | 32 macrocells (MAX architecture) |
| Technology | — | UV-erasable EPROM cell |
| Maximum Counter Frequency (fCNT) | — | [DATA_NEEDED: fCNT in MHz] |
| MIL-STD-883 Screening | — | Class B (DM/883B) |
| Package Type | — | WDIP-28 (ceramic DIP with quartz window) |
| Bilang ng Pin | — | 28 |
| Terminal Form | — | Through-Hole |
| Package Shape | — | RECTANGULAR |
| Programming Method | — | Programmer + UV erase |