EPM5032DI-20 vs EPM5032DI-25 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DI-20 sa pamamagitan ng Intel at EPM5032DI-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5032DI-20 EPM5032DI-25
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 5000 (Altera legacy EPLD) MAX 5000
Architecture CMOS PAL-type EPLD with PIA PAL-type, CMOS, AND-OR sum-of-products
Macrocells 32 32
Dedicated Inputs 7 7
Bidirectional I/O Pins 16 16
Product Terms 320 (maximum) 320
Flip-Flops 16 (one per macrocell) —
Maksimum na Taktiko ng Oras 62.5 MHz —
Pin-to-Pin Delay 20 ns (speed grade -20) —
Packhaging Ceramic DIP-20 (windowed, UV-erasable) Ceramic DIP, windowed (UV-erasable)
Temperature na Operasyon Industrial (per 'I' suffix) 0C to +70C (commercial)
Programming UV-erasable CMOS, JEDEC fuse file —
Development Tool Altera MAX+PLUS II (legacy) MAX+PLUS II / A+PLUS
Tindminan RoHS [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] [DATA_NEEDED: likely non-compliant due to ceramic DIP]
Lead-Free [DATA_NEEDED: lead-free status] —
Device Type — UV-erasable Programmable Logic Device (PLD)
Logic Gates — [DATA_NEEDED: equivalent gate count]
Total Array Inputs — 24
Registered Outputs — 16
Global Clocks — 1
Propagation Delay (tPD) — 25 ns
Maximum Clock Frequency (fMAX) — 62.5 MHz
Volte ng Pagbibigay — 5 V
Process Technology — CMOS
Bilang ng Pin — [DATA_NEEDED: exact pin count - 24 or 28]
I/O Standard — TTL-compatible
Programmability — UV-erasable, EPROM-based
Lifecycle — Not Recommended for New Designs (NRND)

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