EPM5032DI-20 vs EPM5032DI-25 比較
詳細並排比較 EPM5032DI-20 由 Intel 與 EPM5032DI-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032DI-20 | EPM5032DI-25 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | MAX 5000 (Altera legacy EPLD) | MAX 5000 |
| Architecture | CMOS PAL-type EPLD with PIA | PAL-type, CMOS, AND-OR sum-of-products |
| Macrocells | 32 | 32 |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Product Terms | 320 (maximum) | 320 |
| Flip-Flops | 16 (one per macrocell) | — |
| 最大時脈頻率 | 62.5 MHz | — |
| Pin-to-Pin Delay | 20 ns (speed grade -20) | — |
| 封裝 | Ceramic DIP-20 (windowed, UV-erasable) | Ceramic DIP, windowed (UV-erasable) |
| 工作溫度 | Industrial (per 'I' suffix) | 0C to +70C (commercial) |
| Programming | UV-erasable CMOS, JEDEC fuse file | — |
| Development Tool | Altera MAX+PLUS II (legacy) | MAX+PLUS II / A+PLUS |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status for ceramic DIP variant] | [DATA_NEEDED: likely non-compliant due to ceramic DIP] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Gates | — | [DATA_NEEDED: equivalent gate count] |
| Total Array Inputs | — | 24 |
| Registered Outputs | — | 16 |
| Global Clocks | — | 1 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| 供應電壓 | — | 5 V |
| Process Technology | — | CMOS |
| 腳位數 | — | [DATA_NEEDED: exact pin count - 24 or 28] |
| I/O Standard | — | TTL-compatible |
| Programmability | — | UV-erasable, EPROM-based |
| Lifecycle | — | Not Recommended for New Designs (NRND) |