EPM5032LC-20 vs EPM5032PC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032LC-20 sa pamamagitan ng Altera at EPM5032PC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032LC-20 | EPM5032PC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | MAX 5000 |
| Product Type | EPLD / CPLD (One-Time Programmable / UV-Erasable) | — |
| Usable Gates | 600 gates | 600 |
| Macrocells | 32 | 32 |
| Logic Blocks (LABs) | 1 | — |
| Speed Grade | -20 (20 ns pin-to-pin) | — |
| Maximum Frequency | 71.4 MHz | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Supply Voltage (VCC) | 5 V ±5% | 4.75 V to 5.25 V (nominal 5 V) |
| Temperature na Operasyon | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) | [DATA_NEEDED: operating temperature range] |
| Dedicated Inputs | 7 | 24 |
| Bidirectional I/O Pins | 16 | — |
| Total Inputs | 24 | — |
| Output Functions | 16 | — |
| Product Terms per Output | 16 | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Packhaging | LCC-28 (Plastic Leaded Chip Carrier, J-lead) | PDIP-28 (Plastic DIP, 28-pin) |
| Uri ng Pagpapasok | Surface Mount | Through-Hole |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Level ng MSL | [DATA_NEEDED: MSL] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Programming Type | — | OTP (One-Time Programmable) |
| Logic Blocks | — | 2 Logic Array Blocks |
| Product Terms | — | 320 |
| Bidirectional I/O Lines | — | 16 |
| Maksimum na Taktiko ng Oras | — | 62.5 MHz |
| Technology | — | CMOS, 0.65 um process |
| Architecture | — | PAL-type macrocells with Programmable Interconnect Array (PIA) |