EPM5128GC2 vs EPM5128GC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128GC2 sa pamamagitan ng Altera at EPM5128GC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128GC2 EPM5128GC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type EPLD (Erasable Programmable Logic Device) —
Macro Cells 128 —
Usable Gates 2.5K —
Logic Array Blocks (LABs) 8 (16 macro cells each) —
Maximum Internal Frequency 50 MHz —
Supply Voltage VCC 5 V —
I/O Pins 64 —
Dedicated Inputs 16 —
Packhaging Ceramic PGA (GC, windowed) —
Programmable Flip-Flop Modes D / T / JK / SR (selectable) —
Architecture AND/OR plane + programmable macro cell + PIA —
Process Technology CMOS EPROM —
Reprogrammability UV-erasable (windowed ceramic package) —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Tindminan RoHS [DATA_NEEDED: RoHS status] —
Configuration Memory On-chip EPROM (no external boot device) Non-volatile, one-time programmable (erasable via UV)
Bilang ng Pin [DATA_NEEDED: total PGA pin count] —
Logic Elements / Gates — 2,500 usable gates
Macrocells — 128
Number of Usable Gates — 2,500
Maximum Operating Frequency — 50 MHz
Propagation Delay (tPD) — Approx. 25 ns (typical, -2 speed grade)
Supply Voltage (VCC) — 5 V (nominal)
Package Type — 68-pin PGA (Pin Grid Array)
Package Code (per Partstack) — WPGA
Number of Terminals — 68
Programming Technology — UV-erasable EPROM
Grade (per Partstack) — COMMERCIAL
Terminal Form — PIN/PEG

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