EPM5128GC2 vs EPM5128GC-2 比較
詳細並排比較 EPM5128GC2 由 Altera 與 EPM5128GC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5128GC2 | EPM5128GC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | — |
| Macro Cells | 128 | — |
| Usable Gates | 2.5K | — |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | — |
| Maximum Internal Frequency | 50 MHz | — |
| Supply Voltage VCC | 5 V | — |
| I/O Pins | 64 | — |
| Dedicated Inputs | 16 | — |
| 封裝 | Ceramic PGA (GC, windowed) | — |
| Programmable Flip-Flop Modes | D / T / JK / SR (selectable) | — |
| Architecture | AND/OR plane + programmable macro cell + PIA | — |
| Process Technology | CMOS EPROM | — |
| Reprogrammability | UV-erasable (windowed ceramic package) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | — |
| Configuration Memory | On-chip EPROM (no external boot device) | Non-volatile, one-time programmable (erasable via UV) |
| 腳位數 | [DATA_NEEDED: total PGA pin count] | — |
| Logic Elements / Gates | — | 2,500 usable gates |
| Macrocells | — | 128 |
| Number of Usable Gates | — | 2,500 |
| Maximum Operating Frequency | — | 50 MHz |
| Propagation Delay (tPD) | — | Approx. 25 ns (typical, -2 speed grade) |
| Supply Voltage (VCC) | — | 5 V (nominal) |
| Package Type | — | 68-pin PGA (Pin Grid Array) |
| Package Code (per Partstack) | — | WPGA |
| Number of Terminals | — | 68 |
| Programming Technology | — | UV-erasable EPROM |
| Grade (per Partstack) | — | COMMERCIAL |
| Terminal Form | — | PIN/PEG |