EPM5128LC2 vs EPM5128GC2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128LC2 sa pamamagitan ng Altera at EPM5128GC2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5128LC2 | EPM5128GC2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | 8 (16 macro cells each) |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Global Clock Inputs | 1 dedicated | — |
| Propagation Delay (tPD) | 45 ns | — |
| Supply Voltage (VCC) | 5 V | — |
| Process Technology | CMOS EPROM | CMOS EPROM |
| Configuration Memory | On-chip EPROM (non-volatile) | On-chip EPROM (no external boot device) |
| Boundary Scan | JTAG / IEEE 1149.1 | — |
| Temperature na Operasyon | -40 C to +85 C (extended commercial) | [DATA_NEEDED: operating temperature range] |
| Packhaging | PGA (Pin Grid Array, ceramic) | Ceramic PGA (GC, windowed) |
| Uri ng Pagpapasok | Through-Hole / Socketed | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Macro Cells | — | 128 |
| Usable Gates | — | 2.5K |
| Maximum Internal Frequency | — | 50 MHz |
| Supply Voltage VCC | — | 5 V |
| I/O Pins | — | 64 |
| Dedicated Inputs | — | 16 |
| Programmable Flip-Flop Modes | — | D / T / JK / SR (selectable) |
| Architecture | — | AND/OR plane + programmable macro cell + PIA |
| Reprogrammability | — | UV-erasable (windowed ceramic package) |
| Bilang ng Pin | — | [DATA_NEEDED: total PGA pin count] |