EPM5192AGC-15 vs EPM5192-1LC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192AGC-15 sa pamamagitan ng Altera at EPM5192-1LC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192AGC-15 EPM5192-1LC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type EPLD (Erasable Programmable Logic Device) —
Series MAX 5000 —
Macrocells 192 192
Logic Array Blocks 16 (typical for 192-macrocell MAX 5000) —
Maximum User I/O Pins 64 —
Dedicated Inputs 7 —
Total Inputs 72 —
Propagation Delay (tPD) 15 ns (pin-to-pin, -15 speed grade) —
Supply Voltage (VCC) 5 V —
Technology CMOS, UV-erasable EPROM —
Packhaging Ceramic Pin Grid Array (PGA) 64-pin Ceramic J-Lead Chip Carrier (LC)
Programming Method UV erase + EPROM program (via Altera programmer) —
Temperature na Operasyon [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Tindminan RoHS [DATA_NEEDED: RoHS status - legacy ceramic PGA typically non-compliant] Non-compliant (ceramic windowless package, lead-bearing termination)
Katayuan ng Lifecycle Obsolete / Last Time Buy (per Altera legacy product list) —
Family — MAX 5000
Device Type — CPLD (Complex Programmable Logic Device)
Usable Gates — 3,750
Logic Array Blocks (LABs) — 4
User I/O Pins — 64
Maximum Operating Frequency — 62.5 MHz
Propagation Delay (tpd) — [DATA_NEEDED: -1 speed grade tpd in ns]
Volte ng Pagbibigay — 5 V
Process Technology — UV EPROM, erasable windowless
Programmable Interconnect — PIA (Programmable Interconnect Array)
JTAG Boundary Scan — IEEE 1149.1 compliant
Uri ng Pagpapasok — Surface Mount

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