EPM5192AGC84-20 vs EPM5192AJC84-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192AGC84-20 sa pamamagitan ng Altera at EPM5192AJC84-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192AGC84-20 EPM5192AJC84-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type Complex Programmable Logic Device (CPLD) —
Family MAX 5000 MAX 5000
Macrocells 192 192
User I/O Pins 64 —
Dedicated Inputs 7 —
Logic Gates (typical) [DATA_NEEDED: typical gate count] —
Maximum Clock Frequency (fMAX) 66.7 MHz 83.3 MHz
Pin-to-Pin Delay (tPD) 20 ns —
Speed Grade -20 —
Packhaging 84-pin Ceramic Pin Grid Array (CPGA, WPGA) 84-pin PLCC (J84C) windowed ceramic
Package Code WPGA —
Erasure Method UV-Erasable (with OTP window) —
Process Technology CMOS CMOS EPROM
Operating Temperature Grade Commercial —
Volte ng Pagbibigay [DATA_NEEDED: VCC range] —
I/O Standard 5V CMOS / TTL compatible —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] Non-compliant (contains Pb, ceramic windowed package)
Uri ng Pagpapasok Through-Hole (Pin Grid Array socket) Surface Mount
Device Type — EPLD (Erasable Programmable Logic Device)
Propagation Delay (tpd) — 15 ns
Supply Voltage (VCC) — 5 V (single supply)
Technology — CMOS, UV-erasable EPROM
Temperature na Operasyon — [DATA_NEEDED: commercial/industrial/military grade]
Programming Method — UV-erase + EPROM programming (windowed package)
Logic Blocks — 16 Logic Array Blocks (LABs)
I/O Pins — [DATA_NEEDED: user I/O count]

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