EPM5192ALC84-20 vs EPM5192ALC84-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192ALC84-20 sa pamamagitan ng Altera at EPM5192ALC84-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192ALC84-20 EPM5192ALC84-15
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Type UV-Erasable/OTP Complex PLD (EPLD) CPLD / UV-Erasable / OTP Complex PLD
Series Altera MAX 5000 —
Macrocells 192 192
Process Technology CMOS CMOS (EPROM-based)
Speed Grade -20 (20 ns pin-to-pin delay) —
Packhaging 84-pin PLCC (Plastic Leaded Chip Carrier) 84-pin PLCC (QCCJ, J-bend ceramic)
Terminal Pitch 1.270 mm —
Terminal Form J-bend J-BEND
Package Code QCCJ (PLCC-84) QCCJ
Package Shape Square SQUARE
Temperature Grade Commercial —
Programming Method UV-erase + EPROM (One-Time-Programmable option) —
Logic Family MAX 5000 EPLD —
I/O Compatibility TTL-compatible —
Uri ng Pagpapasok Surface Mount (PLCC socket-compatible) —
Configuration Memory EPROM (UV-erasable) —
Tindminan RoHS [DATA_NEEDED: RoHS status not in provided web data] —
Device Family — MAX 5000 (EPM5192)
Dedicated Inputs — 7
User I/O Pins — 64
Propagation Delay (tPD) — 15 ns
Propagation Delay (Industry Variant) — 25 ns (per MicrochipUSA listing)
Supply Voltage (VCC) — 4.75 V to 5.25 V (nominal 5 V)
Programmability — UV-erasable window / OTP
Operating Temperature Grade — Commercial
Architecture — Programmable Logic Array + Macrocell Registers + PIA interconnect

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