EPM5192JC vs EPM5192JC68 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC sa pamamagitan ng Intel at EPM5192JC68 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JC EPM5192JC68
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Product Type CPLD (Complex Programmable Logic Device) EPLD (Erasable Programmable Logic Device)
Series EPM5192 (Classic / MAX-class) —
Macrocells 192 —
Logic Array Blocks (LABs) 12 —
Interconnect Architecture Programmable Interconnect Array (PIA) —
Process Technology CMOS EPROM (UV-erasable) —
Packhaging 68-pin PLCC (JC) windowed ceramic —
Uri ng Pagpapasok Surface Mount Surface Mount (PLCC socket compatible)
Programming Method UV-erase + EPROM programmer —
Non-Volatile Configuration Yes (EPROM cell array) —
Logic Family Classic CPLD (EPM5xxx series) —
Temperature na Operasyon [DATA_NEEDED: commercial / industrial / military grade] 0C to 70C (commercial, JC suffix)
Volte ng Pagbibigay [DATA_NEEDED: VCC nominal] [DATA_NEEDED: VCC]
Propagation Delay [DATA_NEEDED: tpd spec by speed grade] —
Tindminan RoHS [DATA_NEEDED: original Altera marking not RoHS] [DATA_NEEDED: RoHS compliance]
Device Family — MAX 5000
Logic Elements / Macrocells — 192 macrocells
User I/O Pins — 76
Bilang ng Pins — 68
Package Type — PLCC-68 (J-Lead)
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD]
Maximum Frequency (fMAX) — [DATA_NEEDED: fMAX]
Configuration Memory — UV-Erasable EPROM
Programmable Interconnect — Programmable Logic Array + Macrocells
Dedicated Inputs — 12
Clock Pins — 4 dedicated
Programming Tool — MAX+PLUS II (legacy)

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