EPM5192JC vs EPM5192JC68 比較
詳細並排比較 EPM5192JC 由 Intel 與 EPM5192JC68 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192JC | EPM5192JC68 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Product Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Series | EPM5192 (Classic / MAX-class) | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| Interconnect Architecture | Programmable Interconnect Array (PIA) | — |
| Process Technology | CMOS EPROM (UV-erasable) | — |
| 封裝 | 68-pin PLCC (JC) windowed ceramic | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket compatible) |
| Programming Method | UV-erase + EPROM programmer | — |
| Non-Volatile Configuration | Yes (EPROM cell array) | — |
| Logic Family | Classic CPLD (EPM5xxx series) | — |
| 工作溫度 | [DATA_NEEDED: commercial / industrial / military grade] | 0C to 70C (commercial, JC suffix) |
| 供應電壓 | [DATA_NEEDED: VCC nominal] | [DATA_NEEDED: VCC] |
| Propagation Delay | [DATA_NEEDED: tpd spec by speed grade] | — |
| RoHS 狀態 | [DATA_NEEDED: original Altera marking not RoHS] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Logic Elements / Macrocells | — | 192 macrocells |
| User I/O Pins | — | 76 |
| 腳位數 | — | 68 |
| Package Type | — | PLCC-68 (J-Lead) |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: tPD] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fMAX] |
| Configuration Memory | — | UV-Erasable EPROM |
| Programmable Interconnect | — | Programmable Logic Array + Macrocells |
| Dedicated Inputs | — | 12 |
| Clock Pins | — | 4 dedicated |
| Programming Tool | — | MAX+PLUS II (legacy) |