EPM5192LC-25 vs EPM5192LC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC-25 sa pamamagitan ng Altera at EPM5192LC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LC-25 EPM5192LC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type CPLD (Complex Programmable Logic Device) —
Family MAX 5000 MAX 5000
Macrocells 192 192
Logic Elements 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) —
Pin-to-Pin Delay (tPD) 25 ns —
Speed Grade -25 (25 ns) —
Packhaging JLCC-84 (ceramic J-lead chip carrier) PQCC-84 (PLCC-84, J-lead, surface mount)
Uri ng Pagpapasok Surface Mount —
Programmable Technology UV-erasable / OTP (EPROM-based) —
Programming Interface JTAG / Altera programming hardware (legacy) —
Temperature na Operasyon 0C to +70C (commercial) [DATA_NEEDED: commercial/industrial/military grade]
Volte ng Pagbibigay 5 V (typical, MAX 5000) 5 V (typical MAX 5000 family)
I/O Standard TTL-compatible —
Configuration Memory Non-volatile EPROM (on-chip) —
Manufacturer Altera Corporation (now Intel PSG) —
Tindminan RoHS Unknown (legacy ceramic package typically non-RoHS) [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS]
Device Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 12
User I/O Pins — 64
Dedicated Input Pins — 7
External Clock Inputs — 1
Propagation Delay (tPD) — 45 ns (typical, -2 speed grade)
Maximum Internal Frequency — 50 MHz
Interconnect — Programmable Interconnect Array (PIA)
Process Technology — CMOS
Programming — Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG)

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