EPM5192LC-25 vs EPM5192LC-2 比較
詳細並排比較 EPM5192LC-25 由 Altera 與 EPM5192LC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-25 | EPM5192LC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Elements | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) | — |
| Pin-to-Pin Delay (tPD) | 25 ns | — |
| Speed Grade | -25 (25 ns) | — |
| 封裝 | JLCC-84 (ceramic J-lead chip carrier) | PQCC-84 (PLCC-84, J-lead, surface mount) |
| 安裝類型 | Surface Mount | — |
| Programmable Technology | UV-erasable / OTP (EPROM-based) | — |
| Programming Interface | JTAG / Altera programming hardware (legacy) | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: commercial/industrial/military grade] |
| 供應電壓 | 5 V (typical, MAX 5000) | 5 V (typical MAX 5000 family) |
| I/O Standard | TTL-compatible | — |
| Configuration Memory | Non-volatile EPROM (on-chip) | — |
| Manufacturer | Altera Corporation (now Intel PSG) | — |
| RoHS 狀態 | Unknown (legacy ceramic package typically non-RoHS) | [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 64 |
| Dedicated Input Pins | — | 7 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 45 ns (typical, -2 speed grade) |
| Maximum Internal Frequency | — | 50 MHz |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS |
| Programming | — | Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) |