EPM5192LI-1 vs EPM5192JI Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LI-1 sa pamamagitan ng Altera at EPM5192JI sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LI-1 EPM5192JI
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 5000 MAX 5000
Device Type EPLD (UV-Erasable/OTP Complex PLD) EPLD (UV-erasable CMOS Programmable Logic Device)
Usable Gates 3,750 —
Macrocells 192 192
Maximum Toggle Frequency 40 MHz —
Volte ng Pagbibigay 5 V 4.75 V to 5.25 V (nominal 5 V)
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns at -1 grade] —
User I/O Pins [DATA_NEEDED: user I/O count for JLCC variant] 64
Package Type JLCC (windowed, ceramic, UV-erasable) —
Process Technology CMOS EPROM, UV-erasable —
Speed Grade -1 —
Temperature na Operasyon [DATA_NEEDED: industrial vs military range] -40 C to +125 C (industrial, I-suffix)
Bilang ng Pin [DATA_NEEDED: pin count of LI package] —
Uri ng Pagpapasok Surface Mount (JLCC with J-leads) Surface Mount (PLCC socket recommended for UV erasure)
Level ng MSL [DATA_NEEDED: MSL level] —
Tindminan RoHS [DATA_NEEDED: RoHS status of ceramic LI variant] [DATA_NEEDED: RoHS status - pre-2010 part, likely non-compliant]
Lead Free [DATA_NEEDED: lead-free] —
Programmable Interconnect Programmable Interconnect Array (PIA) —
Architecture EEPROM/EPROM-based, non-volatile, instant-on —
Logic Array Blocks (LABs) — 12
Dedicated Inputs — 7
Propagation Delay (tpd) — 55 ns
Technology — CMOS EPROM, UV-erasable
Packhaging — 84-pin PLCC (windowed, J-suffix ceramic)
Programming Method — Altera MAX 5000 programming algorithm (device programmer)
Erasure Method — UV exposure through windowed package

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