EPM7128STC100-10N vs EPM7128STC100-15N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128STC100-10N sa pamamagitan ng Altera at EPM7128STC100-15N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N NrndIntel
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoletePagsanggunian na paghahambing
| Parametro | EPM7128STC100-10N | EPM7128STC100-15N |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Product Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | 8 (16 macro cells each) |
| User I/Os | 84 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Frequency (fMAX) | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (MultiVolt) | — |
| Process Technology | CMOS EEPROM | — |
| Packhaging | 100-pin TQFP (14 x 14 x 1 mm) | 100-pin TQFP |
| Temperature na Operasyon | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | Compliant (Pb-free "N" suffix) | Non-RoHS (legacy SnPb finish typical) |
| Lead-Free | Yes | — |
| Macro Cells | — | 128 |
| Maximum User I/O | — | 84 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns (-15 speed grade) |
| Maximum Internal Frequency | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (VCCIO) | — | 3.3 V or 5 V (per bank) |
| Technology | — | CMOS EEPROM, in-system programmable |
| JTAG (IEEE 1149.1) | — | Yes - in-system programming |
| Output Options | — | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | — | 4 global inputs |
| Katayuan ng Lifecycle | — | Obsolete (PDN effective 2017-06-01) |