EPM7128STC100-10N vs EPM7128STC100-15N 比較
詳細並排比較 EPM7128STC100-10N 由 Altera 與 EPM7128STC100-15N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N NrndIntel
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N Obsolete規格比較
| 參數 | EPM7128STC100-10N | EPM7128STC100-15N |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Product Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | 8 (16 macro cells each) |
| User I/Os | 84 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Frequency (fMAX) | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (MultiVolt) | — |
| Process Technology | CMOS EEPROM | — |
| 封裝 | 100-pin TQFP (14 x 14 x 1 mm) | 100-pin TQFP |
| 工作溫度 | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| 安裝類型 | Surface Mount | — |
| RoHS 狀態 | Compliant (Pb-free "N" suffix) | Non-RoHS (legacy SnPb finish typical) |
| Lead-Free | Yes | — |
| Macro Cells | — | 128 |
| Maximum User I/O | — | 84 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns (-15 speed grade) |
| Maximum Internal Frequency | — | 76.9 MHz |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (VCCIO) | — | 3.3 V or 5 V (per bank) |
| Technology | — | CMOS EEPROM, in-system programmable |
| JTAG (IEEE 1149.1) | — | Yes - in-system programming |
| Output Options | — | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | — | 4 global inputs |
| 生命週期狀態 | — | Obsolete (PDN effective 2017-06-01) |