EPM7128STC100-10N vs EPM7128STC100-15N Comparison
Detailed side-by-side comparison of EPM7128STC100-10N by Altera and EPM7128STC100-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128STC100-10N
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N NrndIntel
EPM7128STC100-15N
EPM7128STC100-15N - 128-Macro Cell CPLD, 15ns, 100-TQFP | Intel / Altera
EPM7128STC100-15N ObsoleteSpecification Comparison
| Parameter | EPM7128STC100-10N | EPM7128STC100-15N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.30 | $9.20 |
| Family | MAX 7000S | MAX 7000S |
| Product Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macrocells | 128 | β |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | 8 (16 macro cells each) |
| User I/Os | 84 | β |
| Propagation Delay (tPD) | 10 ns | β |
| Internal Frequency (fMAX) | 100 MHz | β |
| Supply Voltage (VCCINT) | 5 V | β |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (MultiVolt) | β |
| Process Technology | CMOS EEPROM | β |
| Package | 100-pin TQFP (14 x 14 x 1 mm) | 100-pin TQFP |
| Operating Temperature | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | Compliant (Pb-free "N" suffix) | Non-RoHS (legacy SnPb finish typical) |
| Lead-Free | Yes | β |
| Macro Cells | β | 128 |
| Maximum User I/O | β | 84 |
| Pin-to-Pin Logic Delay (tPD) | β | 15 ns (-15 speed grade) |
| Maximum Internal Frequency | β | 76.9 MHz |
| Supply Voltage (VCC) | β | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (VCCIO) | β | 3.3 V or 5 V (per bank) |
| Technology | β | CMOS EEPROM, in-system programmable |
| JTAG (IEEE 1149.1) | β | Yes - in-system programming |
| Output Options | β | Totem-pole or open-drain (per pin) |
| Dedicated Inputs | β | 4 global inputs |
| Lifecycle Status | β | Obsolete (PDN effective 2017-06-01) |