EPM7256EGC192-12 vs EPM7256EGI192-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256EGC192-12 sa pamamagitan ng Intel at EPM7256EGI192-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM7256EGC192-12 | EPM7256EGI192-15 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 7000 | MAX 7000 |
| Device Logic Cells | 256 macrocells | — |
| Usable Gates | 5,000 | 5,000 |
| Propagation Delay (tPD) | 12 ns | — |
| Maximum Operating Frequency | 90.9 MHz | 76.9 MHz |
| User I/O Pins | 164 | 192 |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Packhaging | 192-pin CPGA (Ceramic Pin Grid Array) | 192-pin CPGA (Ceramic Pin Grid Array) |
| Uri ng Pagpapasok | Through Hole (PGA socket) | Through-Hole (Socket) |
| Technology | CMOS, EEPROM-based | — |
| Temperature na Operasyon | 0C to +70C (commercial) | — |
| Programmable Interface | JTAG (IEEE 1149.1) / ISP | — |
| Logic Blocks (LABs) | 16 | — |
| Macrocells per LAB | 16 | — |
| Tindminan RoHS | Compliant | Non-compliant (ceramic CPGA, contains lead) |
| Lead-Free | Yes | — |
| JEDEC Package Code | S-CPGA-P192 | — |
| Series | — | MAX 7000E |
| Macro Cells | — | 256 |
| Logic Array Blocks (LABs) | — | 16 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Dedicated Input Pins | — | 12 |
| Programmable Power Mode | — | Yes (per-macrocell) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Operating Temperature Grade | — | Industrial (-40C to +85C) |