EPM7256SQC208-7N vs EPM7256SRC208-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7256SQC208-7N sa pamamagitan ng Altera at EPM7256SRC208-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM7256SQC208-7N EPM7256SRC208-10
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 7000S MAX 7000S
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 256 —
Usable Gates 5,000 —
Logic Array Blocks (LABs) 16 —
User I/O Pins 164 —
Speed Grade -7 (7.5 ns pin-to-pin) —
Maximum Frequency 128.2 MHz —
Supply Voltage (VCC) 5 V —
Technology CMOS EEPROM —
Configuration Memory Non-volatile EEPROM (no external config needed) —
Packhaging 208-pin PQFP (Plastic Quad Flat Pack) 208-pin RQFP (BFQFP) exposed pad, 28x28 mm
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon Commercial (0C to +70C) 0C to +70C (TA, commercial)
JTAG Interface IEEE 1149.1 boundary-scan (ISP capable) —
Minimum DC Input Voltage -0.5 V —
Input Undershoot Tolerance -2.0 V for <100 mA, <20 ns —
Tindminan RoHS Compliant (N suffix = lead-free) [DATA_NEEDED: RoHS status]
Pin-to-Pin Delay (tPD) 7.5 ns —
Open-Drain Output Optional per I/O pin —
Number of Macrocells — 256
Number of Logic Array Blocks (LABs) — 16
Number of Gates — 5000
Number of User I/O Pins — 164
Maximum Propagation Delay (tPD) — 10 ns
Maximum Operating Frequency — 100 MHz
Supply Voltage (Internal) — 4.75 V to 5.25 V
Programmable Type — In System Programmable (ISP, JTAG)
Configuration Technology — EEPROM
Terminal Form — Gull Wing
Package Shape — Square
Product Status — Obsolete

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