EPM9320ALC84-15 vs EPM9320LC84-15 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ALC84-15 sa pamamagitan ng Altera at EPM9320LC84-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM9320ALC84-15 EPM9320LC84-15
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 9000 CPLD MAX 9000
Macrocells 320 320
Usable Gates 6000 6,000
Propagation Delay (tPD) 16 ns 15 ns (max)
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 4.75 V to 5.25 V (5.0 V nominal)
User I/O 56 —
Logic Array Blocks (LABs) 16 20
Technology CMOS, EEPROM-based configuration CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX)
Packhaging 84-pin PLCC (S-PQCC-J84, J-lead) 84-pin PLCC (Plastic Leaded Chip Carrier)
Uri ng Pagpapasok Through-hole / socket Surface Mount
Programming Interface JTAG (IEEE 1149.1) / ISP —
Temperature na Operasyon -40C to +85C (industrial) -40C to +85C (commercial) [DATA_NEEDED: exact grade]
Tindminan RoHS [DATA_NEEDED: rohs status] [DATA_NEEDED: confirm from manufacturer]
Level ng Sensitivity sa Asid ng Moisture (MSL) MSL-3 (168 hours per fpgalink.com) —
Lead-Free / Halogen-Free [DATA_NEEDED: lead free status] —
RoHS3 Compliance ROHS3 Compliant (per fpgalink.com listing) —
Series — EPM9320
Device Type — CPLD (Complex Programmable Logic Device)
Maksimum na Taktiko ng Oras — 117.6 MHz
Programmability — 5.0 V in-system programmable (ISP) via JTAG
JTAG Interface — IEEE Std. 1149.1 boundary-scan compliant
Built-in Pull-up Resistors — Yes, on every I/O pin
Architecture Feature — Pin-locking across design iterations

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