EPM9320LC84-20N vs EPM9320ALI84-10N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320LC84-20N sa pamamagitan ng Intel at EPM9320ALI84-10N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM9320LC84-20N - 320-Cell MAX 9000 CPLD, 84-PLCC | Intel / Altera
EPM9320LC84-20N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM9320LC84-20N | EPM9320ALI84-10N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Series | MAX 9000 | — |
| Logic Family | CMOS (EEPROM-based) | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 to 12,000 |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Bilang ng Pins | 84 | — |
| Package Type | Plastic Leaded Chip Carrier (PLCC-84, J-bend) | — |
| Package Code | QCCJ | — |
| Propagation Delay (tPD) | 16 ns | — |
| Internal Frequency | 118 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| Temperature na Operasyon | 0 C to +70 C (Commercial) | -40C to +85C (industrial) |
| Programming | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) | — |
| Uri ng Pagpapasok | Surface Mount (J-bend) | Surface Mount (PLCC socket compatible) |
| Terminal Form | J BEND | — |
| Level ng MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | — |
| Family | — | MAX 9000 |
| Architecture | — | MAX (Multiple Array MatriX), 3rd generation |
| Process Technology | — | CMOS EEPROM |
| Logic Array Blocks (LABs) | — | 20 |
| User I/O Pins | — | 56 |
| Pin-to-Pin Delay | — | 10 ns |
| Maximum Counter Frequency | — | 144.9 MHz |
| VCCINT (Core Supply) | — | 5.0 V |
| VCCIO (I/O Supply) | — | 3.3 V or 5.0 V |
| Input Logic Levels | — | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG) |
| Packhaging | — | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| Configuration Memory | — | EEPROM, non-volatile |