EPM9320LC84-20N vs EPM9320LC84-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320LC84-20N sa pamamagitan ng Intel at EPM9320LC84-15 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM9320LC84-20N - 320-Cell MAX 9000 CPLD, 84-PLCC | Intel / Altera
EPM9320LC84-20N ✓ NakahandaPagsanggunian na paghahambing
| Parametro | EPM9320LC84-20N | EPM9320LC84-15 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Series | MAX 9000 | EPM9320 |
| Logic Family | CMOS (EEPROM-based) | — |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Bilang ng Pins | 84 | — |
| Package Type | Plastic Leaded Chip Carrier (PLCC-84, J-bend) | — |
| Package Code | QCCJ | — |
| Propagation Delay (tPD) | 16 ns | 15 ns (max) |
| Internal Frequency | 118 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V (5.0 V nominal) |
| Temperature na Operasyon | 0 C to +70 C (Commercial) | -40C to +85C (commercial) [DATA_NEEDED: exact grade] |
| Programming | 5.0-V In-System Programmable via JTAG (IEEE 1149.1) | — |
| Uri ng Pagpapasok | Surface Mount (J-bend) | Surface Mount |
| Terminal Form | J BEND | — |
| Level ng MSL | [DATA_NEEDED: MSL moisture sensitivity level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: confirm from manufacturer] |
| Family | — | MAX 9000 |
| Logic Array Blocks (LABs) | — | 20 |
| Maksimum na Taktiko ng Oras | — | 117.6 MHz |
| Programmability | — | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | — | IEEE Std. 1149.1 boundary-scan compliant |
| Packhaging | — | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Technology | — | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | — | Yes, on every I/O pin |
| Architecture Feature | — | Pin-locking across design iterations |